Building a Better Bathtub: Computing at the Optical Memory Interface

To fully exploit the high bandwidth and inherent parallelism of optical memory systems, it is necessary to perform correspondingly parallel computations at or near the interface to the memory system. In this paper, we present a system in which a dynamically reconfigurable processor is built at the optical memory interface. Dynamically reconfigurable processors exploit parallelism at the level of individual machine instructions. They are based on the time multiplexing of gate array logic between various processor configurations, each of which is matched to a particular required computation. This paper is an analysis of the performance of an optically reconfigurable processor in comparison to conventional multiple instruction issue processors. We will show that the volume of configuration data required makes these systems difficult to build in electronic implementations but ideal for implementations with optical memory.